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LE25S40MB
Figure 2 Block Diagram
X-
4M Bit
ADDRESS
BUFFERS
DECODER
Flash EEPROM
Cell Array
&
LATCHES
Y-DECODER
CONTROL
LOGIC
SERIAL INTERFACE
I/O BUFFERS
&
DATA LATCHES
CS
SCK
SI
SO
WP
HOLD
Table 1 Pin Description
Symbol
SCK
SI
SO
CS
WP
HOLD
VDD
VSS
Pin Name
Serial clock
Serial data input
Serial data output
Chip select
Write protect
Hold
Power supply
Ground
Description
This pin controls the data input/output timing.
The input data and addresses are latched synchronized to the rising edge of the serial clock, and the data is
output synchronized to the falling edge of the serial clock.
The data and addresses are input from this pin, and latched internally synchronized to the rising edge of the
serial clock.
The data stored inside the device is output from this pin synchronized to the falling edge of the serial clock.
The device becomes active when the logic level of this pin is low; it is deselected and placed in standby
status when the logic level of the pin is high.
The status register write protect (SRWP) takes effect when the logic level of this pin is low.
Serial communication is suspended when the logic level of this pin is low.
This pin supplies the 1.65 to 1.95V supply voltage.
This pin supplies the 0V supply voltage.
No.A2096-3/22
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